1. Technical Field of the Invention
The present invention relates to a circuit and method for triggering control circuitry in a memory device, and particularly to a sense circuit and method for enabling boost circuitry of the memory device based upon the activity of sense amplifiers thereof.
2. Background of the Invention
Today's dynamic random access memory (DRAM) devices typically include at least one memory cell array organized in rows and columns of capacitive-storage memory cells, with each row of memory cells being connected to a distinct word line and each column of memory cells being connected to a distinct bit line. Address decode circuitry is included to select a word line based upon the value of the address provided to the DRAM device. A distinct sense amplifier is connected to each pair of bit lines and amplifies the differential voltage placed thereon from accessing a row of memory cells.
In executing a memory access operation, such as a read, write or refresh operation, a word line is selected and driven to the power supply voltage value, Vdd, so that the contents of the memory cells in the selected row of memory cells are placed upon the bit lines of the DRAM device. When the sense amplifiers are powered up and connected to the bit lines, boost circuitry is enabled to capacitively boost the selected word line to a boosted voltage in excess of the power supply voltage value. With the voltage on the selected word line being at the boosted voltage, a charge corresponding to the power supply voltage may be capacitively stored in a memory cell in the selected row to refresh the contents of the memory cell. Storing a charge corresponding to the power supply voltage, as opposed to a charge corresponding to a lesser voltage value as would occur without boost circuitry, advantageously lengthens the amount of time until the capacitive memory cell needs to be refreshed.
During a memory access operation, any line that can capacitively couple to the selected word line can conceivably change the voltage and/or charge appearing thereon. This may undesirably alter the value of the boosted voltage to which the selected word line is to be later capacitively boosted.
Sense amplifiers are typically powered up and/or connected to high reference voltage level Vdd and low reference voltage level Vss during a memory access operation and particularly immediately following the selected row of memory cells being connected to the bit lines. Because the number of sense amplifiers that are simultaneously powered up and/or turned on may exceed one thousand, an appreciable amount of noise, in the form of a voltage spike or pulse, is typically generated by powering the sense amplifiers. The extent of the noise generated from powering the sense amplifiers has been seen to substantially effect the ability of the boost circuitry to boost the voltage appearing on the selected word line to the desired voltage level.
Based upon the foregoing, there is a need for a circuit and method for reducing the effects of noise on the operation of a DRAM device and particularly the operation of the boost circuitry thereof.